system verilog - How to implement Summation equation in SystemVerilog constraints? -


c=∑(a[i]*b[i]) consider 2 arrays , b. result,c of mac operation of 2 arrays , b should less 1024. use systemverilog constraints implement above condition. size of 2 arrays can go 1 n , each array element stores 1 byte. have randomize both arrays.

now i've seen solution in chat, i'll give thinking

constraint c_sum { c == a.sum() (a[item.index] * b[item.index]); c < 1024;}

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